1. Technical Field
This invention generally relates to integrated circuits, and more specifically relates to application-specific integrated circuits (ASICs) which have one or more embedded microprocessor cores, which allow for testing the microprocessor core with standard test vectors, and which allow for using an in-circuit emulator (ICE) in debugging the software for each microprocessor core.
2. Background Art
Modern electronic systems often incorporate embedded microprocessors or microcontrollers. With the push for higher levels of integration and performance, the trend has been to embed a microprocessor or microcontroller (referred to hereinafter generically as "microprocessor) within an application specific integrated circuit (ASIC). The resulting ASIC contains the microprocessor "core" plus application-specific logic packaged on a single chip.
Since the microprocessor core within an ASIC typically interfaces only to logic within the ASIC, it is typically not necessary during normal operation to connect input/output (I/O) signals from the microprocessor core to the primary I/O (i.e., off-chip) drivers/receivers of the ASIC. However, when microprocessor I/O is not accessible outside of the ASIC chip, the microprocessor core within the ASIC becomes much more difficult to test. Typically, stand-alone microprocessors are tested by applying a set of test vectors to the inputs, and monitoring the outputs for expected responses. These sets of test vectors are often referred to as Architectural Verification Patterns (AVPs). When the microprocessor is embedded within ASIC logic, it is no longer possible to use the AVPs developed for the stand-alone microprocessor. New AVPs, which account for the behavior of the embedded microprocessor plus the application-specific logic, could be developed. However, this would require new and unique AVPs for each ASIC. The development of AVPs for a semiconductor device is a very expensive and time-consuming process, and generating new AVPs for each ASIC device would thus substantially increase the development costs for each device. It is therefore desirable to provide a way to test a microprocessor core implemented within an ASIC using the standard AVPs developed for the stand-alone microprocessor.
Another complication that results from embedding a microprocessor core in an ASIC relates to the testing of the software that runs on the embedded microprocessor core. Typically, software for microprocessors is tested and integrated with the hardware using a test tool called an in-circuit emulator (ICE). An ICE typically has connection points which are coupled to the connections points of the microprocessor, and which emulates microprocessor operation while providing advanced debugging capabilities. A stand-alone microprocessor may thus be removed in an embedded system and replaced with an ICE during the debugging of the system hardware and software. However, when a microprocessor is implemented within an ASIC, the connection points to the microprocessor are buried within the ASIC logic. One way to use an ICE with a microprocessor embedded within an ASIC is to bring all the microprocessor I/O to external I/O pins on the ASIC device. However, for most applications, the majority of microprocessor I/O signals are not needed at the external I/O pins during normal operation. Adding all the microprocessor I/O signals as I/O pins on the ASIC device, which are used only during development of the ASIC, would greatly increase the packaging size for the ASIC, thereby substantially increasing its cost. This method of providing external I/O pins on an ASIC for using an ICE with an embedded microprocessor generally is not a cost-effective solution. In addition, for applications that require two or more embedded microprocessor cores within an ASIC, providing all the appropriate microprocessor I/O signals on external I/O pins would result in an unworkable number of I/O pins.
Various architectures are known for embedding a microprocessor core within an ASIC. For example, U.S. Pat. No. 5,254,940 "Testable Embedded Microprocessor and Method of Testing Same" (issued Oct. 19, 1993 to Oke et al. and assigned to LSI Logic Corp.) discloses a method of embedding a microprocessor core such that microprocessor I/O are driven off-chip only when the ASIC is configured into a special test mode. FIG. 1 herein is a reproduction of FIG. 2 in the Oke et al. patent. During normal operation, chip output pads 214 are used for signals to/from the application-specific logic. This circuit 200 permits the embedded microprocessor 204 to be tested using the standard AVPs developed for the stand-alone microprocessor. The Oke et al. circuit is limited, however, in that an ICE cannot be substituted for the embedded microprocessor. In addition, the Oke et al. circuit is limited to unidirectional signals, and does not provide a solution for bidirectional I/O lines.
Another design for embedding a microprocessor within an ASIC is described in U.S. Pat. No. 5,304,860 "Method for Powering Down a Microprocessor Embedded within a Gate Array" (issued Apr. 19, 1994 to Ashby et al. and assigned to Motorola, Inc.). FIG. 2 herein is a reproduction of FIG. 7 of the Ashby et al. patent. The Ashby et al. patent describes a method of embedding the microprocessor core such that the embedded microprocessor core and the application-specific logic can be isolated from each other. The circuit of Ashby et al. permits the embedded microprocessor core to be tested using standard AVPs, and permits the connection of an ICE to emulate the embedded microprocessor. The circuit is limited, however, in making all microprocessor I/O signals coupled to the application-specific logic accessible to I/O pins during all modes of operation. The increased I/O pin requirement typically increases the size of the chip, the size of the package, and hence the cost of the ASIC. The problem of excessive pinout becomes even more significant for ASICs that have more than one embedded microprocessor core. Another significant disadvantage is that all connections between the embedded microprocessor and the application-specific logic is always via an off-chip driver 54 and matching receiver 58. The propagation delay of an off-chip driver and receiver is much greater than the propagation delay of on-chip signals. Thus, making all connections between the microprocessor core and the application-specific logic through off-chip drivers and receivers imposes a significant performance limitation due to increased propagation delays.
Another relevant architecture for an integrated circuit that includes an embedded microprocessor is disclosed in U.S. Pat. No. 5,331,571 "Testing and Emulation of Integrated Circuits" (issued Jul. 19, 1994 to Aronoff et al. and assigned to NEC Electronics, Inc.). The three patents listed above are incorporated herein by reference. The Aronoff et al. circuit allows for testing an embedded microprocessor, but requires internal three-state busses (i.e., three-state busses which connect logic entirely inside the chip). Internal three-state busses do not allow for complete testability of the integrated circuit. For example, if a three-state driver is turned off when it should be turned on, its output may still float to a logic state that is indicative of a functioning circuit, thereby masking defects in the integrated circuit.
Therefore, there existed a need to provide an integrated circuit, such as an ASIC, with an embedded microprocessor core that allows for the microprocessor core to be tested using standard AVPs developed for the stand-alone microprocessor, that allows for an ICE to be used to emulate the embedded microprocessor core, that couples the microprocessor core directly to the application-specific logic without passing through off-chip drivers and receivers, and that contains no three-state devices to assure complete testability.